The present invention generally relates to field effect transistors and more particularly to a metal-insulator-semiconductor (MIS) transistor having increased conductance between the source and drain regions.
Typical MOS transistors uses a semiconductor substrate in which a source region and a drain region are defined in the semiconductor substrate at opposite sides of a channel region also defined in the substrate. A gate insulator is provided on the channel region and a gate electrode is provided on the gate insulator and thus above the channel region. When a number of such MOS transistors are assembled on a common semiconductor substrate, as in the case of a large scale integrated circuit (LSI), there appears a leakage path between the MOS transistors formed in the substrate. Such a leakage path deteriorates the operation of the MOS transistors and hence the operation of the integrated circuit.
In a conventional LSI, the MOS transistors are isolated from each other by providing a field insulator region between the transistors. Such an insulator region is formed by oxidization of surface of the substrate. However, the field insulator region for isolating the MOS transistor occupies a large area on the substrate and presents the problem that the number of the MOS transistors which can be assembled on the LSI is reduced.
On the other hand, there is another type of MOS transistor having a so-called semiconductor-on-insulator (SOI) structure in which the transistor is formed on an insulator. Referring to FIG. 1 showing a typical example of such a MOS transistor having the SOI structure, the transistor comprises a silicon single crystal film 1 provided in the form of an island on an insulator layer 2 formed on a substrate 3. Because of this reason, the silicon single crystal film 1 will be referred to as a silicon island 1. The silicon island 1 is divided into a source region 1a and a drain region 1b with a channel region therebetween which is covered by a gate insulator 4. Further, a gate electrode 5 is provided so as to cover the gate insulator 4. The gate electrode 5 extends from the silicon island 1 and forms a gate contact area 5' on the insulator layer 2 for contact with a wiring electrode. In such an SOI structure, each MOS transistor is provided on the insulator layer 2 and the problem of isolation of plural transistors is eliminated.
FIG. 2 shows a cross section of the silicon island 1 taken along a line 3--3', of FIG. 1. Referring to FIG. 2, a channel 4a for passing carriers through the silicon island 1 from the source region 1a to the drain region 1b (see FIG. 1) is formed immediately below the gate insulator 4. It should be noted that the gate width which is defined as the width of the silicon island 1 measured perpendicularly to the gate length of the MOS transistor, is represented by W.sub.O and the height of the gate defined as the height of the silicon island 1, is represented by W.sub.H.
In such a conventional MOS transistor having the SOI structure, there is a problem in that the total current which can flow between the source region and the drain region is limited by the cross sectional area of the channel 4a. As the channel 4a is formed immediately below the gate insulator 4 in the form of thin layer, the overall cross sectional area of the channel 4a is approximated by the total gate width WG which is represented by using the gate width W.sub.O and the gate height W.sub.H, as WG=W.sub.O +2W.sub.H. In order to increase the current or the conductance between the source and of the gate width W.sub.O or the size of the gate height W.sub.H. However, such an increase results in an increase in the size of the MOS transistor which is undesirable from the view point of assembling the MOS transistors in an LSI form.
FIG. 3 shows another prior art MOS transistor proposed to solve the aforementioned problem. In FIG. 3, parts corresponding to those parts in the preceding drawings are given identical reference numerals and the description thereof will be omitted.
Referring to FIG. 3 showing the cross section of this another prior art MOS transistor device, there is provided another gate electrode 6 directly on the insulator layer 2 which in turn is formed on the substrate 3 similarly to the previous case. The gate electrode 6 is buried under an insulator layer 7 and a silicon island 10 is provided on the insulator layer 7. The silicon island 10 is covered by the gate insulator 4 except for its bottom surface, which is in contact with the insulator layer 7 and a pair of doped regions 10a and 10b, which are formed in the silicon island 10 as the source and drain regions. These source and drain regions 10a and 10b are connected to wiring electrodes through respective contact holes (not shown) provided in the gate insulator 4. Similarly to the device of FIG. 1, the gate electrode 5 is provided on the gate insulator 4. Further, the silicon island 10 is buried under an insulator layer 8 together with the gate insulator 4 and the gate electrode 5.
In this prior art transistor, there is formed a channel 4b along the bottom of the silicon island 10 in correspondence to the gate electrode 6 and another channel 4c along the top of the silicon island 10 in correspondence to the gate electrode 5. As the channels are formed along the top and bottom of the silicon island 1, the overall cross sectional area of the channel is nearly doubled and the conductance of the MOS transistor is increased correspondingly.
However, even with such a structure, it is easily understood that there is a practical limitation in the increase in the conductance of the transistor because of the resulting excessive increase in the size of the transistor. Further, such a transistor has a problem in that the structure becomes complex and needs many steps in manufacturing.